1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a 3D (three-dimensional) semiconductor apparatus in which a plurality of chips are stacked, and a semiconductor system using the same.
2. Related Art
In order to elevate the degree of integration of a semiconductor apparatus, there has been developed a three-dimensional (3D) semiconductor apparatus in which a plurality of chips are stacked and packaged in a single package. Recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which silicon vias are formed through a plurality of stacked chips so that all the chips are electrically coupled with one another.
In order to use power with a low level and reduce power consumption, a wide input/output (IO) semiconductor apparatus having an increased input/output number has been developed. The wide IO semiconductor apparatus uses a scheme in which the number of input/output lines or terminals is significantly increased to lower an operational frequency and increase a bandwidth thereof.
FIG. 1 is a diagram schematically illustrating the configuration of a semiconductor apparatus 10 according to the conventional art. In FIG. 1, the semiconductor apparatus 10 may include first and second chips CHIP1 and CHIP2. The first and second chips CHIP1 and CHIP2 include first and second through vias 11 and 12 and input/output circuits I/O, respectively. The first and second through vias 11 and 12 extend through the first and second chips CHIP1 and CHIP2 to electrically couple the first and second chips CHIP1 and CHIP2 to each other through bumps 13, respectively. The input/output circuits I/O are electrically coupled to the first and second through vias 11 and 12, respectively. Signals inputted to first and second input/output terminals DQ<0> and DQ<1> may be inputted to internal circuits of the first and second chips CHIP1 and CHIP2 through the first and second through vias 11 and 12, respectively. Data outputted from the first and second chips CHIP1 and CHIP2 may be outputted to the first and second input/output terminals DQ<0> and DQ<1> through the first and second through vias 11 and 12, respectively.
The semiconductor apparatus 10 has a structure in which all signal lines including the through vias are short-circuited, and has a fixed number of input/output lines or terminals. That is, input/output circuits I/O of the first and second chips, which are electrically coupled to the same through via, may not simultaneously operate. Furthermore, the semiconductor apparatus 10 does not have a redundancy through via for signal path repair when the through via or the bump has failed.
FIG. 2 is a diagram schematically illustrating the configuration of another semiconductor apparatus 20 according to the conventional art. In FIG. 2, the semiconductor apparatus 20 may include first and second chips CHIP1 and CHIP2, wherein the first chip CHIP1 may include first and second through vias 21 and 22, and an input/output circuit I/O, and the second chip CHIP2 may include third and fourth through vias 23 and 24, and an input/output circuit I/O. The semiconductor apparatus 20 has a structure capable of increasing the number of input/output lines or terminals.
The first and second through vias 21 and 22 electrically couple the first and second chips CHIP1 and CHIP2 to each other through bumps 25, respectively. The third through via 23 is electrically coupled to the second through via 22, and the second via 22 is electrically coupled to a first input/output terminal DQ1<0> through the input/output circuit I/O of the first chip CHIP1. The fourth through via 24 is electrically coupled to the first through via 21 and the input/output circuit I/O of the second chip CHIP2, and is electrically coupled to a second input/output terminal DQ2<0> through the first through via 21. Since the semiconductor apparatus 20 has independent signal paths for the input/output circuits I/O of the first and second chips CHIP1 and CHIP2, it is possible to increase the number of input/output lines or terminals twice as compared with that of the semiconductor apparatus 10 of FIG. 1. However, as illustrated in FIG. 2, the signal path from the third through via 23 to the second through via 22 is not utilized.